1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a device formation section (or region) and an alignment mark section on a semiconductor substrate.
2. Background Art
In recent years, semiconductor devices have become smaller and smaller as their integration density has increased and each semiconductor region of the devices has been miniaturized. The transistor characteristics of a miniaturized semiconductor device is significantly affected by the alignment between the active regions and the gate electrodes, as described in detail below.
Each gate electrode (of a semiconductor device) is formed on a predetermined area of an active region. Therefore, when the gate electrode material is patterned, it is necessary to carry out the process of aligning the gate electrode material with the active regions.
One method for such alignment is to detect the alignment marks under the gate electrode material by passing light through the material. However, general-purpose memories such as DRAMs (Dynamic Random Access Memories), SRAM (Static Random Access Memories), and flash memories use polycide or polymetal as their gate electrode material, which makes it difficult to detect the alignment marks since these materials have a high light reflectance level.
To overcome the above problem, a step (or a height difference) is formed in the alignment mark section to facilitate the alignment, as described in Japanese Laid-Open Patent Publication No. 11-87488 (1999).
Description will be made of a conventional method for manufacturing a semiconductor device with reference FIGS. 28 to 37. It should be noted that in these figures, like numerals will be used to denote like components.
First of all, a silicon oxide film 62 and a silicon nitride film 63 are sequentially formed on a semiconductor substrate 61, as shown in FIGS. 28A to 28C. Then, active region patterns are formed on the semiconductor substrate 61 by use of a photolithographic technique. Specifically, first a resist pattern 64 is formed on the silicon nitride film 63. It should be noted that FIG. 28A, 28B, and 28C show the portions of the resist pattern (64) in the alignment mark section, the memory cell section, and the peripheral circuit section, respectively.
Then, the silicon nitride film 63 is etched using the resist patterns 64 as a mask, forming a silicon nitride film pattern 65 as a hard mask. After removing the resist pattern 64, which is no longer necessary, the semiconductor substrate 61 is etched using the silicon nitride film pattern 65. Then, a silicon oxide film 67 is formed on the inside walls of grooves 66 by the thermal oxidation method, producing the structures shown in FIGS. 29A to 29C.
Then, a silicon oxide film 68 is formed on the silicon nitride film pattern 65 such that it fills the grooves 66, and polished by the CMP (Chemical Mechanical Polishing) method, producing the structures shown in FIGS. 30A to 30C. In these figures, the top surface 68a of the silicon oxide film 68 and the top surface 65a of the silicon nitride film pattern 65 are in the same plane.
After wet-etching the silicon oxide film 68 by use of hydrofluoric acid, the silicon nitride film pattern 65 is removed since it is no longer necessary. This produces the structures shown in FIGS. 31A to 31C. These figures show a step(s) 69 having a height of h′ formed at the boundary between the silicon oxide film 68 and the silicon oxide film 62.
Then, channel doping is applied to the semiconductor substrate 61 to set the well for each transistor and the transistor threshold value. Specifically, impurities of a first or second conductive type are ion-implanted in desired areas using resist patterns formed by a photolithographic technique as masks.
For example, as shown in FIGS. 32A to 32C, a resist pattern 70 is formed on all sections except for the NMOS region of the peripheral circuit section (shown in FIG. 32C). Then, impurity ions are implanted in the NMOS region using the resist pattern 70 as a mask. After removing the resist pattern 70, which is no longer necessary, a resist pattern 71 is formed on all sections except for the PMOS region of the peripheral circuit section (shown in FIG. 33C), as shown in FIGS. 33A to 33C. Then, impurity ions are implanted in the PMOS region using the resist pattern 71 as a mask. After that, the resist pattern 71 is removed since it is no longer necessary. Then, as shown in FIGS. 34A to 34C, a resist pattern 72 is formed on all sections other than the memory cell section (shown in FIG. 34B). After implanting impurity ions in the memory cell section using the resist pattern 72 as a mask, the resist pattern 72 is removed since it is no longer necessary.
After the above ion implantation, a resist pattern 73 is formed on all sections other than the alignment mark section, as shown in FIGS. 35A to 35C. Then, the silicon oxide films 62, 67, and 68 are removed through wet-etching using the resist pattern 73 as a mask. After that, the resist pattern 73, which is no longer necessary, is removed, producing the structures shown in FIGS. 36A to 36C.
Furthermore, after removing the silicon oxide film 62 by wet-etching, a gate insulation film material 74, a gate electrode material 75, a hard mask material 76, and a resist film 77 are laminated in that order, producing the structures shown in FIGS. 37A to 37C.
In FIGS. 37B and 37C, the surface of the silicon oxide film 68 buried in the grooves in the memory cell section and the peripheral circuit section and the surface of the gate insulation film material 74 formed on the semiconductor substrate 61 together form a substantially flat surface even though there exist some small steps at the boundary between them. Therefore, the surfaces of the gate electrode material 75 and the hard mask material 76 formed on the above substantially flat surface are also substantially flat.
On the other hand, as shown in FIG. 37A, since the silicon oxide film 68 is not formed on the groove in the alignment mark section, the gate insulation film material 74, the gate electrode material 75, and the hard mask material 76 are formed along the groove, forming a concave portion. That is, formation of such a big step (concave portion) in the alignment mark portion facilitates detection of the alignment marks. Therefore, the resist film 77 can be patterned at a desired position, allowing the gate electrodes to be formed at desired positions.
The above conventional method, however, requires the process shown in FIGS. 35 and 36 to form a step in the alignment mark section. That is, after implanting ions in the peripheral circuit section and the memory cell section, a resist pattern having an opening over the alignment mark section must be formed, and then the silicon oxide films in the alignment mark section must be removed using the resist pattern as a mask. As a result, the total number of processes required greatly increases, leading to the problem of a reduction in the throughput, cost, yield, etc.